1. Field of the Invention
The present invention relates to semiconductor devices having chip-on-chip structures for three-dimensionally laminating semiconductor chips via on-chip capacitors. In particular, the present invention relates to techniques for reducing feed noises while increasing on-chip capacitances.
The present application claims priority on Japanese Patent Application No. 2008-2536, the content of which is incorporated herein by reference.
2. Description of Related Art
Semiconductor memories having chip-on-chip (COC) structures have been developed to meet requirements for achieving high performance (e.g. for increasing storage capacities) and for size reduction (e.g. for improving packaging densities).
A typical example of a semiconductor device having a chip-on-chip (COC) structure is designed to laminate a plurality of semiconductor memories (e.g. semiconductor chips serving as dynamic random-access memories) with a controller (i.e. a semiconductor chip for controlling semiconductor memories). The controller is formed in the lowermost layer of the COC structure, while the semiconductor memories are sequentially laminated above the controller. Each of the semiconductor memories has a plurality of through-electrodes.
The controller feeds electric power to each of the semiconductor memories via the through-electrodes which are electrically connected to metal bumps. Electric power is supplied to the semiconductor memories in the order from the lowermost one to the uppermost one.
Various techniques for reducing feed noises in semiconductor devices not having COC structures have been developed and disclosed in various documents such as Patent Document 1, which teaches a semiconductor integrated circuit device having a plurality of operational circuits sharing an external capacitor for the purpose of a reduction of feed noise.    Patent Document 1: Japanese Unexamined Patent Application Publication No. H01-95643
The present inventor has recognized that the above noise reduction technique suffers from the following problem and is not applicable to semiconductor devices having COC structures.
Generally speaking, it is difficult to design semiconductor devices having COC structures in consideration of severe requirements for reducing feed noises, wherein feed noises increase in response to increasing the currents consumed in semiconductor memories, and wherein noise margins decrease in response to decreasing the drive voltages in the recent developments of semiconductor manufacturing processes.
It is possible for semiconductor devices having COC structures to reduce feed noises by use of on-chip capacitors mounted on semiconductor chips laminated together.
Since semiconductor devices having COC structures are designed to feed electric power to semiconductor chips in the order from the lowermost one to the uppermost one, semiconductor chips formed in lower layers have a high priority in feeding electric charge thereto; hence, it is difficult to feed electric charge to semiconductor chips formed in upper layers.
To solve the problem, it is necessary to increase electrostatic capacitances of on-chip capacitors mounted on semiconductor chips; but this increases the overall layout area for mounting semiconductor chips, thus pushing up manufacturing cost.
Because of the above reason, it is necessary to develop a feasible technique for substantially reducing feed noise while increasing electrostatic capacitances of feed lines with low cost and without increasing the overall layout area of semiconductor chips.